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San Jose, California, February 25 – 29, 2024
(The following diary appeared first as a daily blog at life.lithoguru.com and is reproduced here in a slightly edited form.)
SPIE
Advanced Lithography and Patterning Symposium 2024 – day 0
The
2024 SPIE Advanced Lithography and Patterning Symposium is 6
conferences, 3 plenary talks, 1 special session, 2 panel sessions,
15 short courses, and 1 poster session, and it starts Monday in San
Jose, California. Abstract
submittals were 215, about the same as last year, and registration
is up about 15% from last year, to 2,200.
That is right at the historical average for the ten years
prior to Covid. It is
good to be back!
I am
beginning the week relaxed, for a change.
For more than 30 years I have spent the Sunday before the
start of the conference teaching an eight-hour short course (and for
some of those years, 12 hours).
I love to teach, but I am not as young and energetic as I
used to be. Standing and
talking all day is exhausting, so finally I decided that is not how
I wanted to start my week.
Instead, I took a class!
(Thank you, Ofer Adan, for a great course on metrology tool
matching.) So as Sunday
comes to a close, I am relaxed and ready for any exciting week
discovering what is new in lithography, patterning, metrology, and
more.
SPIE
Advanced Lithography and Patterning Symposium 2024 – day 1
Monday
began with awards, as always.
The new group of SPIE fellows from the lithography community
had a very international flavor this year:
Soichi Inoue (Kioxia), Myungjun Lee (Samsung), Ted Liang
(Intel), Mark van de Kerkhof (ASML), and Jan Van Schoot (ASML).
Congratulations!
The Nik Cobb Memorial Scholarship was presented to Nicholas Jenkins
of the University of Colorado at Boulder.
I was
extremely happy to see that Richard Sandstrom is this year’s winner
of the Frits Zernike Award for Microlithography, our community’s
highest honor. Richard
got his PhD from the University of California San Diego in 1979 and
seven years later co-founded Cymer with his college friend Bob
Akins. Richard was chief
scientist and their excimer lasers quickly became industry enablers
for 248 and then 193 nm lithography.
I think it was only two years after the founding of Cymer
when they shipped their first excimer light source.
The development of the EUV light source was also directed by
Sandstrom, though it took a bit longer!
These light sources have always been critical to the success
of Moore’s Law and lithography’s role in it, and Richard’s
contribution for over 30 years was seminal.
Congratulations!
It was
good to welcome Todd Younkin back to this conference.
He abandoned the field of lithography after ten years at
Intel to become the CEO of SRC (Semiconductor Research Corporation),
and his talk focused on SRC’s role in charting a sustainable future
for semiconductors.
The
industry giant Gordon E. Moore died last March at the age of 94.
His influence on the lithography community was profound (his
insights that became Moore’s Law, the founding of Intel, even his
1995 plenary talk at this conference) and so the symposium decided
to remember him with a very special Tribute Session.
Harvey Fineberg, President of the Gordon and Betty Moore
Foundation, gave a video speech about his ongoing legacy of
charitable contributions.
Craig Barrett, former Intel CEO, provided many moving stories
about his times with Moore, and their joint love of fishing.
A main theme: while a very quiet man, when Gordon Moore
spoke, people listened.
Paolo Gargini, former Director of Technology Strategy at Intel,
provided a personalized history of Moore’s role in Moore’s Law (in
classic Gargini style:
80+ slides in 20 minutes).
Dan Hutcheson of Tech Insights described Moore as a “gentle
giant” that believed in the fundamentals.
Dan provided my favorite quote of the day: “Moore’s Law is
about us and our ability to innovate.
It is not a law; it is an opportunity.”
Finally, Burn Lin and Martin van den Brink tied Moore’s Law
to our community by giving each their own take on the history of
lithography. It was a
great tribute. (Aside:
the announcement of Martin van den Brink’s imminent retirement from
ASML provoked a standing ovation for his contributions to our
community.)
The
regular conference talks began in the afternoon, and I started with
an invited talk by Andras Vladar (NIST) commemorating the 40-year
anniversary of the first CD-SEM (introduced by Hitachi in 1984).
I agree with him when he said there are no low hanging fruits
for improving SEM technology, but there are fruits.
The future of SEM technology in the semiconductor industry
“is bright.”
The end
of the talks on Monday is always a highlight for me, since it marks
the beginning of the Fractilia Happy Hour – thanks to everyone who
came!
SPIE
Advanced Lithography and Patterning Symposium 2024 – day 2
The
plenary session was split into two days this year, with two
plenaries on Tuesday morning.
Ann Kelleher of Intel talked about her view of the new era of
Moore’s Law: system technology co-optimization (STCO).
This is in addition to, not replacing, the prior eras of
geometric scaling and design technology co-optimization (DTCO).
The new Moore’s Law metric is not the number of transistors
on a chip, but the number of transistors in a package, with a goal
of one trillion by 2030.
Some quotes from her presentation that stood out for me:
“DSA
(directed self-assembly) is a key innovation that needs to be
brought to high volume manufacturing.”
“The
line between silicon and advanced packaging is blurring.”
Intel
has been promoting their catch-up plan for close to two years now –
five nodes in five years, culminating in the Intel 14A node, before
starting back to a more relaxed two-year cadence.
But interestingly, the 14A node is expected to have a
transistor density that is only 1.2X the 18A node.
In the past we might have called that a half-node, or even a
shrink version of the existing node.
But maybe this is the new normal – smaller node-over-node
improvements.
Chan
Hwang of Samsung gave a plenary on lithography for memory
production. He spoke
about many things that are front and center in my mind, especially
contact hole edge placement error (EPE) and one of its largest
components, local critical dimension uniformity (LCDU).
For EUV, the key to success is controlling LCDU at low dose.
Since the knobs for lowering stochastic LCDU are limited,
their focus is on reducing global CDU to give more budget for LCDU.
Later
in the morning there were several papers on a topic that has been
bedeviling EUV lithography for some time:
image fading due to mask 3D effects.
For the case of dipole illumination (needed for the tightest
pitches), the mask 3D effect causes a phase shift between the two
diffraction orders, which results in an image shift.
Since the right pole shifts the vertical lines in one
direction and the left pole shifts them in the oppositive direction,
the result is an unshifted image with lower contrast and image
log-slope. The best
long-term solution is to lower the mask 3D effects using new mask
absorber materials, but that is still some years away.
In the meantime, Eelco van Setten of ASML described details
of one proposal to add aberrations to compensate for this phase
shift. Of course, this
makes many people nervous (we’ve been working on lowering
aberrations for decades), especially since most masks include both
tight-pitch lines and spaces plus other patterns that would be
harmed by such aberrations.
Jieun Song of Samsung used a more traditional approach –
source mask optimization (SMO), this time for staggered arrays of
holes with the goal of reducing LCDU.
I have to admit, though, that this has a similar downside of
being ideal only for the tight pitch holes and not for the other
patterns on the mask.
Emily
Gallagher ended the morning in the Optical and EUV Nanolithography
conference with a talk about how mask roughness transfers to the
wafer. This topic has
been around for many years (I wrote my first paper on it in 2009),
but imec has taken a novel approach.
They programmed “random” roughness on the mask (not square
waves of different amplitudes and periods that others have done in
the past). Jogs of
various lengths and widths allowed control of both the mask LER and
its correlation length.
Both the mask and the wafer printed with it were then measured.
I look forward to studying the results in more detail when
the paper is published.
In the
afternoon I gave my first talk of the week, but it followed right
after Gurpreet Singh of Intel described the use of DSA rectification
combined with EUV to print 21 nm and 18 nm pitch patterns using what
is called self-aligned litho-etch-litho-etch (SALELE, pronounced
“sah-lee-lee”). He has
been promoting this approach for a few years now, and this year
including yield and electrical resistance data for the metal layer
it was used on. Compared
to EUV-only patterning, the DSA approach produced extremely better
yield and performance at the 18 nm pitch (and was easier to control
at the 21 nm pitch). The
results are quite impressive.
My
paper immediately followed and was an EPE analysis of data from that
same Intel process (Gurpreet was a coauthor).
Using the EPE modeling approach that I introduced last year,
measurements of the stochastics of the DSA line/space patterning and
the alternative EUV-only patterning were combined with measurements
of the via patterning that contacts with these metal lines to
predict failure rate (in particular, the probability that a via
would short to a neighboring line).
This enabled the modeling of the overlay process window
(OPW), the range of overlay errors that can be tolerated while
keeping the failure rate below some maximum allowed.
This approach translates the measurements of stochastics
(such as LCDU or LEPE) into more tangible benefits such as the size
of the OPW. The results
explained the yield behavior seen in Gurpreet’s prior paper, making
our two papers a tandem endorsement for this DSA process.
I was
coauthor on another Intel paper that afternoon as well, this one
given by Pulkit Saksena.
Call me biased, but I thought Pulkit’s paper was great.
(Let me get the obvious pun out of the way:
I was biased, but Pulkit’s roughness measurements were not.)
He explained how Intel uses Fractilia’s MetroLER for material
selection (main message, you must include etch in the evaluation,
and PSDs (the power spectral density of the roughness data) are key
to understanding the different between after litho and after etch
roughness. He then
showed how the NILS difference between two scanner illumination
sources did not predict the roughness difference that resulted
(again, PSDs were useful in diving into the details).
Finally, he talked about EUV scanner matching.
Three scanners running the same process with the same mask
had matched CDs (for three different pitches), but not matched LWR
(the biggest difference was at the smallest pitch).
For the three scanners there was a 7% range in unbiased LWR
for 32 nm pitch single-print patterns.
I think this is the first time anyone has reported such a
difference between EUV tools, but I suspect others will be
investigating this kind of matching soon.
In the
metrology session at the end of the day there were several talks
about using high-voltage CD-SEMs to measure two layers at once,
allowing direct measurement of in-die EPE.
I think this approach is a great complement (but not a
replacement) for the indirect EPE modeling that I talked about in my
paper earlier in the day.
The last talk I saw was Jack Wong of IBM looking at the
sources of NZO (the non-zero offset between optical scribe-line
measurement of overlay after development compared to the in-die
measurement of device overlay after etch).
His definition of NZO was a mean plus three-sigma value, and
in my mind, it is the three-sigma (what I call NZO variability) that
is the biggest worry.
His sources of variation analysis was quite nice.
As
always on Tuesday night I experienced the hospitality of my friends
at the resist companies (plus KLA) – thank you!
SPIE
Advanced Lithography and Patterning Symposium 2024 – day 3
Wednesday was the peak of busy for me, attending many papers (and
giving one). It was also
a very typical day in that almost all of the papers I saw were
exactly what I expected:
incremental advances. Nothing
jaw dropping, just the small advances that have fueled this
industry’s progress for the 40 years I have been involved.
Jodi
Grzeskowiak of TEL did a great job explaining their new
“anti-spacer” process, using acid diffusion into a resist pattern to
form a skin that turns into a negative tone version of a spacer
pattern. She described
it as a “track-based pitch split.”
I was especially happy that the process didn’t have a cute
acronym with a trademark symbol and no description of how it worked.
Indira
Seshadri of IBM showed off what IBM is good at, optimizing all
aspect of a process (in this case the Lam dry resist) to get high
yield at tight pitches.
Hyeon Bo Shim of Samsung provided a simple geometric model for how
electrons escape out of a contact hole (for the case of vertical
sidewalls only), showing that the aspect ratio controls the
visibility of the hole bottom.
Since I am a coauthor (with Ben Bunday) on a paper on a
similar topic on Thursday, I was especially interested.
I’ve already checked out this Samsung geometric model against
our SEM simulations and it works surprisingly well.
Boris
Habets (KLA) collected overlay data on the “micron scale”.
He was able to measure overlay directly on the device, but
did so in a memory cell so that he could achieve extremely high
sampling over length scales we don’t normally interrogate.
Over a distance of a few microns overlay variations are not
due to scanner effects, but rather shorter-range proximity effects.
In this case, each memory array tile (a few microns square)
had a regular signature, possibly due to film stress relaxation.
The magnitude was a few tenths of a nanometer, but if stable
and consistent would be correctable on the mask.
I
attempted to attend the panel discussion on the future of EUV
lithography, but was unsuccessful.
The event was standing room only, and I was unwilling the
elbow my way through the crowd standing three deep at the door.
I hope it was useful.
I did make it to the poster session, however, and actually
walked the whole circuit.
There were some nice posters and a fun crowd.
SPIE
Advanced Lithography and Patterning Symposium 2024 – day 4
The
final day! In the
morning I watched the ASML updates on their EUV and DUV systems,
working backwards from high-NA EUV.
Two high-NA systems are being put together almost
simultaneously, one at the High-NA demonstration lab in Veldhoven,
and one at Intel in Portland.
These tools should start running wafers at resolution “in a
few weeks or months”, according to Jara Garcia-Santaclara.
Since design work began in 2014, a 10-year idea-to-print
cycle is pretty good for a tool of this complexity.
On the low-NA EUV front, the new NXE:3800 has started
shipping (though none are yet running at a customer site), with a
25% increase in source power and other changes to increase
throughput and performance.
Anyone who has been paying attention knows that financial analysts have
been coming regularly to this symposium for at least 20 years.
The consequences are never good.
Companies that care about their stock price (and that would
be all companies that have a stock price) often require their
authors to provide messages that they want to give to Wall Street,
regardless of how it plays to the lithography community.
A perfect example was Peter Klomp, who gave a good talk on
ASML’s low-NA EUV tools.
But it was padded with 6 or 8 slides at the front that were
completely unnecessary for the lithography community and sounded
like the kind of thing a CEO would say at the start of an investors’
day event. Data is
growing! AI is coming!
People need more chips!
Ah well.
Yoji
Watanabe of Nikon talked about their development of maskless DUV
projection systems (both 248 and 193nm) using a digital mirror
spatial light modulator in place of the mask.
They have a proof-of-concept system running, and some of its
parameters were revealed.
It has a 193 nm wavelength with NA = 0.675.
The reduction ratio is “greater than 100” resulting in an
exposure field less than 1 mm wide.
The pixel size at the wafer is 40 nm, and the current
throughput is 0.5 wafers per hour.
Obviously all of these things will evolve (smaller pixel
size, larger field size, higher throughput) as development proceeds,
but the initially images looked pretty good.
There are definitely some devices where mask costs exceed
most all other costs, so I can see the benefits of such a maskless
system.
Chris
Anderson of xLight shed some light on that start-up’s audacious
plans for building Free Electron Laser (FEL) light sources for EUV
manufacturing. While
everything they have is still only on paper (they are shooting for
first light in 2027), he described a centralized FEL (a pair of them
actually) that could feed up to 20 EUV scanners with 2kW of power
(4X greater than the brightest sources currently available from
ASML). The cost of one
of these sources would be about $500M (give or take a few $100M), so
that is a pretty big bet, especially since ASML will get to decide
if xLight even has a chance to compete.
After
zipping over to the Directed Self-Assembly (DSA) session in the
Novel Patterning conference, I learned from Lander Verstraete of
imec that contact hole rectification with DSA is great in about all
respects except one – local pattern placement error (LPPE).
While local CD Uniformity (LCDU) significantly improves after
applying DSA (enabling low-dose EUV printing of the original holes),
the LPPE gets worse.
Further optimization is required – I doubt it is a fundamental
problem. Tomoshiro Iwaki
of Micron spoke about using DSA with 9X multiplication (3X pitch
division in both X and Y) when printing staggered arrays of holes.
Iwaki-san presented a year’s worth of 1b DRAM yield data, showing an improvement up to the current 88.5% yield.
Still, the process is not in high-volume manufacturing for
reasons that Iwaki-san was a bit cagey about, but I think related to
the pattern placement error of the holes.
Rober
Browning of Intel gave a short but sweet talk on using the Applied
Materials Sculpta tool to shrink tip-to-tip spacing for the case of
trenches (common to damascene metal layers).
The tool uses physical etching at an angle to preferentially
increase etch bias in only one direction, and Intel used it to grow
the length of a space without growing its width.
In Intel’s case they were able to replace an EUV double
exposure process with a single exposure + Sculpta.
Very interesting, and it sounded like Intel has proven out
its potential.
I left
the conference to go home a few hours early, and so missed some good
papers (including one I was a coauthor on with Ben Bunday).
As always, it was a fun but exhausting week.
The mood was upbeat, as the industry recovers from its 2023
doldrums. 2024 is off to
a good start!
Chris Mack is a writer and lithographer in Austin, Texas.
© Copyright 2024, Chris Mack.
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